Thanh Dat Bui
I am an incoming PhD student in Computer Science at Clemson University, where I will work with Dr. Zhenkai Zhang on systems and hardware security. I recently completed a B.S. in Electronics and Telecommunications Engineering at the University of Science, VNUHCM.
My background combines hands-on digital design with systems-level study: FPGA prototyping, DMA/controller design, Linux-capable RISC-V SoCs, hardware verification, and communication-system analysis. My current independent study focuses on computer architecture, GPU architecture, memory-system behavior, and cache or memory side channels.
I am broadly interested in the intersection of computer architecture, system security, and practical hardware evaluation, especially where low-level mechanisms shape both performance and isolation.
Research
My work so far sits between hardware implementation and system-level reasoning: building and validating digital systems, then studying the architectural and security consequences of how those systems behave.
Independent Study in Computer Architecture and Hardware Security
Structured pre-doctoral study aligned with GPU systems security, covering operating systems, computer systems, computer architecture, vector/GPU architecture, and cache or memory side channels. Current reading and notes focus on memory hierarchy behavior, GPU isolation, and microarchitectural attack surfaces.
CESLAB, HCMUS-VNUHCM
Contributed to the design, implementation (Verilog), FPGA verification, hardware debugging, and system integration of hardware accelerators and SoC components. This work included Linux-capable RISC-V SoCs, FPGA bring-up, and custom DMA peripherals integrated into Nios V-based systems.
Current Research Directions
- Computer architecture and memory-system behavior
- GPU architecture and hardware isolation
- FPGA prototyping, verification, and system bring-up
- SoC design and integration, especially RISC-V-based platforms
- Practical hardware evaluation for security and performance questions
Selected Preparation
- Computer Architecture: A Quantitative Approach
- Operating Systems: Three Easy Pieces
- Computer Systems: A Programmer’s Perspective
- Weekly technical reports and slide notes on architecture and side-channel papers
Selected Projects
Open-Source RISC-V SoC Implementation with DNN Acceleration
Designed, implemented, and verified a Linux-capable RISC-V SoC on a Xilinx VC707 FPGA using Chipyard. Integrated a Gemmini-based DNN accelerator through the RoCC interface and carried the system from Chisel/Scala generation to Debian Linux boot on hardware.
Design and Integration of a Custom DMA Controller on FPGA
Designed a Verilog DMA controller with Avalon-MM interfaces, integrated and tested it on an Intel DE10-Standard FPGA board, wrote C-based transfer tests, and documented the implementation and validation workflow in a formal internship report.
Communication-System Analysis Projects
Built MATLAB-based analyses for digital and wireless communication systems, including A-law and μ-law companding, SQNR evaluation, and QPSK equalization under frequency-selective AWGN channels using ZF and MMSE methods with constellation and eye-diagram analysis.
Selected Publications
- Nguyen, NH., Dang, TP., Bui, TD., Hoang, TT., Pham, CK., Huynh, HT. (2024). Designing and Implementing a 2D Integer DCT Hardware Accelerator Fully Compatible with Versatile Video Coding. ICCSA 2024 Workshops. DOI
- Nguyen, NH., Dang, TP., Tran, TK., Bui, TD., Hoang, TT., Huynh, HT. (2024). A Configurable 2D-Integer DCT Hardware Accelerator Compatible with H.266 Standard based on RISC-V Architecture. ISRITI 2024. DOI
- Huynh, TMT., Tran, TK., Bui, TD., Pham, CK., Huynh, HT. (2025). An Efficient Algorithm Compatible with Low-performance Hardware for AI Edge Devices in Arrhythmia Prediction. ICISN 2025.
- Pham, DH., Huynh, TMT., Tran, TK., Bui, TD., Pham, CK., Huynh, HT. (2025). Efficient AI Model and Hardware Architecture Based on CNN for Arrhythmia Prediction. ICDV 2025.
CV & Resume
I maintain both a fuller academic CV and a shorter industry-focused resume.